Signal processors spend a significant portion of time and resources moving data, shuffling it in preparation for manipulation. This inefficiency can be significantly reduced for downstream DSP processors by using a large, multi-ported memory buffer tightly integrated with a user-programmable FPGA logic block and a corner-turning Direct Memory Access (DMA) engine. This allows DSP and other processors to spend a higher percentage of time and resources on intelligent data manipulation, reducing overhead and system complexity. This article examines design issues and technology advances that can increase efficiency and optimize performance.