VPX has become the defacto standard for the current generation of military embedded computing platforms. These systems include high-speed serial fabrics such as Serial RapidIO, PCI Express, or Ethernet.

The initial VPX standards have focused on Gen1 Serial RapidIO, Gen 1 PCIe, and XAUI with maximum baud rates of 2.5 to 3.125Gbaud, Even supporting these rates is not a simple task often requiring a detailed signal integrity analysis and careful attention to the overall loss budget and the numerous signal impairments to insure success first time out. The new VITA 65 OpenVPX standard plans to add options for 5 and 6.25Gbaud as well in order to support Gen2 Serial RapidIO and Gen 2 PCIe.

The recent adoption of IEEE 802.3ap 10GBASE-KR, and the availability of silicon transceiver devices from a number of silicon vendors including AMCC, Broadcom, and Xilinx, provides the basis for the next increment in VPX performance. This is the first standard communication protocol to support 10Gbaud per pair operation over a backplane so it is a natural next step for VPX to implement 10GBASE-KR for rugged applications. 10GBASE-KR will require a signal integrity analysis paradigm shift from the classic time domain approaches (e.g. eye diagrams) to frequency domain and statistical approaches. Gen2 Serial RapidIO and Gen 2 PCIe include some of this thinking, but 10GBASE-KR takes it to a whole new level.

Designing a compliant inter-operable channel for 10.3Gbaud over a single lane on a typical VPX backplane poses a number of technical challenges. This paper evaluates a representative VPX channel for 10GBase-KR compatibility using the IEEE 802.3ap compliance metrics. The tools and techniques for simulating a 10Gbaud channel will be discussed.